1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, in particularly to, a ferroelectric random access memory. The present invention is used in a mobile product such as a cellular mobile telephone, a wireless tag, an IC card, a game machine, and the like.
2. Description of the Related Art
As a ferroelectric random access memory (FeRAM) using a ferroelectric capacitor, the present inventor proposes a scheme of a chain structure in Jpn. Pat. Appln. KOKAI Publication Nos. 10-255483, 11-177036, and 2000-22010. In the ferroelectric random access memory, a cell transistor and a ferroelectric capacitor are connected in parallel to each other to constitute one memory cell. In the ferroelectric random access memory using this scheme, a memory cell having a small size, a planar transistor which can be easily manufactured, a versatile high-speed random access function, and the like can be realized.
A ferroelectric random access memory having a folded bit line configuration is known. In this ferroelectric random access memory, array noise caused by on from the word lines, the plate lines, the substrate, and the like can be reduced. However, noise caused by a parasitic capacity between bit lines in different bit line pairs cannot be reduced.
As a scheme which can be applied to reduce noise caused by the parasitic capacitor between bit lines in a ferroelectric random access memory, a scheme described in H. Hidaka et al., IEEE Journal of Solid-State Circuit, Vol. 24, No. 1, pp. 21–27, February 1989 or H. Hirano et al., IEEE Journal of Solid-State Circuit, Vol. 32, No. 5, May. 1997 are known. In H. Hidaka et al., noise is reduced by twisting bit lines in the folded bit line configuration. In this scheme, however, since a twist region is secured, a chip size increases by about several percentages, and an effect of reducing a power consumption cannot be achieved.
In H. Hirano et al., only a selected column (bit line pair) in the memory cell array is activated. In this scheme, a power consumption of the memory cell array can be suppressed. Since cell data is not read from unselected bit line pairs located both the sides of the selected bit line pair, the unselected bit line pairs can be used for a shielding purpose. As a result, noise caused by a parasitic capacity between bit lines can be reduced. However, as a first problem, some sense amplifier circuits are activated, and the remaining sense amplifier circuits are inactivated. For this reason, decode circuits achieved by column addresses are required for all the sense amplifier circuits to increase the number of elements. As a second problem, although a low power consumption can be realized, column addresses must be decoded, and therefore, date except for limited data cannot be read or written outside the chip, and a bandwidth is limited. As a third problem, memory cells of columns except for a selected column must be inactivated, a plate drive circuit and plate lines must be arranged on the same side as that of a sense amplifier circuit to complicate the circuit. As a fourth problem, since a plate line connected to a memory cell at a row address except for a selected row address is inactivated, an unselected memory cell is disadvantageously disturbed.
The present inventor has proposed a method of reducing noise from a selected bit line pair and a sense amplifier circuit connected thereto, and a unselected bit line pair and a sense amplifier circuit connected thereto in a configuration obtained by alternately arranging bit line pairs and sense amplifier circuits connected thereto (U.S. Patent application. No. 2004/0105293).
In the ferroelectric random access memory having a chain structure, it is assumed that word lines and plate lines are arranged in a direction perpendicular to bit lines, that data of only one bit line is read every four bit lines, and that data of the other bit lines are not read. In this case, in general idea, memory cells of four types are necessary. In addition, four plate lines and four word lines are arranged on one memory cell, and each one plate line and word line must be activated every four plate lines and four word lines to considerably increase a cell size.